1. Field of the Invention
The present invention relates to a non-volatile dynamic random access memory (hereinafter, referred to as NV-DRAM) device, for example, to an NV-DRAM device having a volatile operation mode and a non-volatile operation mode, and to another NV-DRAM device having only a non-volatile operation mode.
2. Description of the Related Art
NV-DRAM devices are divided into two types: (a) a memory device having memory cells formed of a ferroelectric material for performing writing and reading by polarity inversion of the ferroelectric material (described in Nikkei Microdevices, June 1991, pp. 78-86); and (b) a memory device having a volatile operation mode and a non-volatile operation mode.
The memory device of (b) is divided into two types depending on the material used. One is a memory device having memory cells, each of which includes a DRAM unit (for the volatile operation mode) and an EEPROM (electrically erasable programmable read only memory) unit (for the non-volatile operation mode). Such a device performs the volatile mode operation and the non-volatile mode operation. The other is a memory device which has memory cells formed of a ferroelectric material and is performed in different operation modes depending on whether the polarity of the ferroelectric material is inverted or not inverted. In the case where the polarity is not inverted, the volatile mode operation is performed, and in the case where the polarity is inverted, the non-volatile mode operation is performed.
The former is described in detail in U.S. patent application Ser. No. 07/549,293, and the latter is described in Nikkei Microdevices, June 1991, pp. 78-86.
In practice, a volatile operation mode refers to DRAM operations including reading, writing and refreshing operations; and a non-volatile operation mode refers to a recall operation and a store operation.
FIG. 9 is a block diagram of a conventional NV-DRAM device 100 having a volatile operation mode and a non-volatile operation mode.
The NV-DRAM device 100 includes, as input pins, a Vcc pin, an NE pin (an enable pin for switching the NV-DRAM device 100 to a non-volatile mode), a CE (chip enable) pin, an OE (output enable) pin, and a We (write enable) pin. A usual memory operation and a recall operation shown in FIG. 10 are performed by way of control signals sent to the input pins from a microprocessor.
FIG. 10 is a timing chart: for the recall operation. A voltage Vcc is applied from a power supply to the Vcc pin, and a LOW signal is inputted to the NE pin at a timing shown in FIG. 10. While the signal at the NE pin is kept LOW (namely, for 10 ms), the recall operation is performed for all bits. Upon completion of the recall operation, a HIGH signal is inputted to the NE pin to reset the NV-DRAM device 100 in the recall state.
To the CE pin, the OE pin, and the WE pin, signals are inputted in waveforms shown in FIG. 10.
A period during which data is stored in an EEPROM unit of each memory cell depends on the amount of charges leaked from the floating gate of the memory cell. Accordingly, an attempt to securely store the data for a long period of time, for example, ten years, inevitably results in a decline in the production yield.
In a memory device having memory cells formed of a ferroelectric material, data can be stored for approximately one year, currently. An attempt to extend the period to ten years also results in a decline in the production yield. (An NV-DRAM device utilizing the polarity inversion of a ferroelectric material is described in detail in Nikkei Microdevices, June 1991, pp. 78-86 and in Gekkan Semiconductor World, May 1990, pp. 118-125.)
As is apparent from the above description, both types of conventional memory devices mentioned above have problems in the production yield and improvement in reliability of data.
Another example of an NV-DRAM device having memory cells, each including a non-volatile unit and a volatile unit has been proposed by the applicant of the present invention in Japanese Patent Application No. 2-202958.
FIG. 11 is a block diagram of the NV-DRAM device described in the above application. Since an overall construction of the NV-DRAM device described in the above application is similar to NV-DRAM devices according to the present invention, FIG. 11 will also be used in the description of examples of the present invention. The NV-DRAM device includes a memory array 1, a read/write timing circuit 4, a recall timing circuit 5, a store timing circuit 6, and an input circuit 11. The input circuit 11 changes the potential when receiving a signal from an external apparatus. The NV-DRAM device further includes a recall/store logic circuit 9 and a recall/store latch circuit 10 both as operation state holding means, and a power supply voltage monitoring circuit 12.
The memory array 1 includes a plurality of memory cells arranged on a chip, the memory cells each including a combination of a DRAM unit 1a and an EEPROM unit 1b. The read/write timing circuit 4 receives a CE (chip enable) signal, an NE (non-volatile enable) signal, an OE (output enable) signal, and a WE (write enable) signal from the external apparatus through the input circuit 11, and performs a reading, writing or refreshing operation of data in the DRAM units 1a of the memory cells of the memory array 1 sequentially in accordance with the level (HIGH or LOW) of the signals.
For which memory cell the read/write timing circuit 4 performs the reading, writing or refreshing operation is designated by an address counter 8 updated by a timer 7 or an external address (not shown; for example, an external address pad). In practice, in the state where a REC (recall enable) signal and an STR (store enable) are not latched by the recall/store latch circuit 10, if the CE signal is LOW, the OE signal is LOW, and the WE signal is HIGH, the reading operation is performed. If the CE signal is LOW, the OE signal is HIGH, and the WE signal is LOW, the writing operation is performed. If the CE signal is LOW, the OE signal is HIGH, and the WE signal is HIGH, the refreshing operation is performed.
In the state where the REC signal is latched by the recall/store latch circuit 10, if the CE signal is HIGH, and the OE signal is LOW, the recall timing circuit 5 sequentially performs the recall operation of the data in the memory cells of the memory array 1. The recall operation is performed page by page. Namely, data in the memory cells connected to one word line addressed by the address counter 8 are recalled at a time.
The store timing circuit 6 receives the STR signal from the recall/store latch circuit 10, and performs a store operation of data simultaneously in all the memory cells of the memory array 1 based on a generation timing of the STR signal. Upon completion of the store operation, the store timing circuit 6 sends a store operation termination pulse .phi..sub.2 to the recall/store latch circuit 10.
The power supply voltage monitoring circuit 12 sends a power-on detection pulse .phi..sub.1 to the recall/store latch circuit 10 when the power is turned on. The power-on detection pulse .phi..sub.1 indicates that the recall operation should be performed. When the power supply voltage is decreased to a specified value or lower (including when the power is off), the power supply voltage monitoring circuit 12 sends a power-off detection pulse .phi..sub.3 to the recall/store latch circuit 10. The power-off detection pulse .phi..sub.3 indicates that the store operation should be performed. The power supply voltage monitoring circuit 12 has, for example, a configuration as shown in FIG. 12.
As is shown in FIG. 12, NMOS transistors 161 and 162 and a resistance 163 are connected in series between the power supply and the ground. A resistance 164 and an NMOS transistor 165 are connected in series between the power supply and the ground. Further, a junction point J.sub.1 of the NMOS transistor 162 and the resistance 163 is connected to a gate of the NMOS transistor 165, and a junction point J.sub.2 of the resistance 164 and the NMOS transistor 165 is connected to an inverter 166, which is connected to an inverter 167 in series.
In the above-mentioned configuration, when the power is off, the transistor 165 is also off, and the potential of the junction point J.sub.2 is at the ground level. When the power is turned on from such a state, the potential of the junction point J.sub.2 is raised immediately. Subsequently, the NMOS transistors 161 and 162 are turned on, thereby raising the potential of the junction point J.sub.1 Accordingly, the NMOS transistor 165 is turned on, thereby lowering the potential of the junction point J.sub.2 to the ground level. Thus, the power-on detection pulse .phi..sub.1 is sent to the recall/store latch circuit 10 through the inverters 166 and 167.
Again with reference to FIG. 11, the recall/store logic circuit 9 receives the CE signal, the NE signal, the OE signal, and the WE signal from the external apparatus through the input circuit 11. When the CE signal is HIGH, the NE signal is LOW, the OE signal is HIGH, and the WE signal is LOW, the recall/store logic circuit 9 sends a store operation initiation signal .phi..sub.4 to the recall/store latch circuit 10. The store operation initiation signal .phi..sub.4 indicates that the store operation should be initiated.
When the CE signal is LOW, the NE signal is HIGH, the OE signal is HIGH, and the WE signal is HIGH, the recall/store logic circuit 9 sends a recall latch reset signal .phi..sub.5 to the recall/store latch circuit 10. The recall latch reset signal .phi..sub.5 indicates that the recall operation should be terminated. When the CE signal is HIGH, the NE signal is LOW, the OE signal is LOW, and the WE signal is HIGH, the recall/store logic circuit 9 sends a recall latch set signal .phi..sub.6 to the recall/store latch circuit 10. The recall latch set signal .phi..sub.6 indicates that the recall operation should be initiated. The signals .phi..sub.4, .phi..sub.5, and .phi..sub.6 are relatively short, pulse-like signals.
FIG. 13 is a detailed diagram of the recall/store latch circuit 10. The recall/store latch circuit 10 includes a store latch section 110 and a recall latch section 130. A detailed configuration and operation of each section will be described, hereinafter.
In the store latch section 110, inverters 113 and 114 are connected in inverse parallel to each other. An NMOS transistor 111 and an NMOS transistor 112 are connected in parallel between a junction point J.sub.3 of the inverters 113 and 114 and the ground. The NMOS transistors 111 and 112 are driven by the power-on detection pulse .phi..sub.1 and the store operation termination pulse .phi..sub.2 respectively. NMOS transistors 115 and 116 are connected in parallel between a junction point J.sub.4 of the inverter 114 and another inverter 119 and the ground. The NMOS transistor 115 is driven by the power-off detection pulse .phi..sub.3 through a pulse generating circuit 117, and the NMOS transistor 116 is driven by the store operation initiation signal .phi..sub.4 through a pulse generating circuit 118.
The junction point J.sub.4 is connected to an output terminal T.sub.1 of the store latch section 110 through the inverter 119, a NAND circuit 121 and an inverter 122. When the power-on detection pulse .phi..sub.1 or the store operation termination pulse .phi..sub.2 is inputted, the inverters 113 and 114 respectively maintain the potential at the junction point J.sub.3 at the ground level and the potential at the junction point J.sub.4 at the Vcc level. When the power-off detection pulse .phi..sub.3 or the store operation initiation signal .phi..sub.4 is inputted, the inverters 113 and 114 respectively maintain the potential at the junction point J.sub.3 at the Vcc level and the potential at the junction point J.sub.4 at the ground level.
The NAND circuit 121 receives the potential at the junction point J.sub.4 inverted by the inverter 119, and also receives the REC signal, from the recall latch section 130, inverted by an inverter 120. Accordingly, only when the REC signal is not outputted (at the LOW level) from the recall latch section 130, the store latch section 110 can maintain the STR signal at the output terminal T.sub.1 (at the HIGH level).
In the recall latch section 130, inverters 139 and 140 are connected in inverse parallel to each other. NMOS transistors 137 and 138 are connected in parallel between a junction point J.sub.5 of the inverters 139 and 140 and the ground. The NMOS transistor 137 is driven by the recall latch reset signal .phi..sub.5 through a pulse generating circuit 135, and the NMOS transistor 138 is driven by the store operation initiation signal .phi..sub.4 through a pulse generating circuit 136. An NMOS transistor 141, an NMOS transistor 142 and an NMOS transistor 143 are connected between a junction point J.sub.6 of the inverter 139 and an inverter 134 and the ground. The NMOS transistor 141, the NMOS transistor 142, and the NMOS transistor 143 are driven by the store operation termination pulse .phi..sub.2, the power-on detection pulse .phi..sub.1 and the recall latch set signal .phi..sub.6, respectively.
The junction point J.sub.6 is connected to an output terminal T.sub.2 of the recall latch section 130 through the inverter 134, a NAND circuit 132 and an inverter 131. When the recall latch reset signal .phi..sub.5 or the store operation initiation signal .phi..sub.4 is inputted, the inverters 139 and 140 respectively maintain the potential at the junction point J.sub.5 at the ground level and the potential at the junction point J.sub.6 at the Vcc level. When the store operation termination pulse .phi..sub.2, the power-on detection pulse .phi..sub.1, or the recall latch set signal .phi..sub.6 is inputted, the inverters 139 and 140 respectively maintain the potential at the junction point J.sub.5 at the Vcc level and the potential at the junction point J.sub.6 at the ground level.
The NAND circuit 132 receives the potential at the junction point J.sub.6 inverted by the inverter 134, and also receives the STR signal, from the store latch section 110, inverted by an inverter 133. Accordingly, only when the STR signal is not outputted (at the LOW level) from the store latch section 110, the recall latch section 130 can maintain the REC signal at the output terminal T.sub.2 (at the HIGH level).
As is shown in FIG. 11, the REC signal and the STR signal are outputted to the recall timing circuit 5 and the store timing circuit 6, respectively, without inversion, and are also outputted to the read/write timing circuit 4 through inverters 20 and 21. Accordingly, either one of the three timing circuits, namely, the store timing circuit 6, the recall timing circuit 5, and the read/write timing circuit 4 is allowed to operate depending on whether the REC signal is maintained at the output terminal T.sub.2, the STR signal is maintained at the output terminal T.sub.1, or neither the STR signal nor the REC signal is maintained. In these cases, the other two circuits are prohibited from operating.
As is aforementioned, in the NV-DRAM device proposed by the applicant of the present invention in Japanese Patent Application No. 2-202958, once a recall operation is selected, the recall state is maintained until the recall/store latch circuit 10 as an internal recall latch circuit is reset by external control signals such as the CE signal, the NE signal, the OE signal and the WE signal.
In order to protect the data stored in the EEPROM section 1b by an unintentional store operation, it is required that the recall operation is performed for all the desired memory cells of the memory array 1 when the power is turned on.
In the above NV-DRAM device proposed by the applicant of the present invention, the recall state is maintained from the time when the recall/store latch circuit 10 is set by the power-on detection pulse .phi..sub.1 detected by the power supply voltage monitoring circuit 12 until the recall/store latch circuit 10 is reset by the external control signals such as the CE signal. The recalled data does not appear in an output pad until the data is read out from the DRAM unit 1a.
In a system including a great number of such NV-DRAM devices, once the recall/store latch circuits 10 of the NV-DRAM devices are set when the power is turned on, the NV-DRAM devices performing the recall operation and the NV-DRAM devices performing the volatile mode operation (or the store operation) are both existent in the system until the recall/store latch circuits 10 of all the NV-DRAM devices are reset by the aforementioned external control signals.
In order to make such a system easier to use, it is preferable to have a construction in which the recall operation is performed for all the desired memory cells when the power is turned on, and the recall state is automatically released upon completion of the recall operation, whereby all the NV-DRAM devices in the system are put into the volatile operation mode. The following (1) and (2) are the reasons.
(1) Since DRAM devices have been used more widely than NV-DRAM devices, it is preferable to provide the NV-DRAM devices with a DRAM operation mode in terms of compatibility.
(2) In general, the recall operation and the volatile operations have different time periods for a cycle. Therefore, a system in which NV-DRAM devices have different operation modes is time-consuming and inefficient.
For the above-mentioned reasons, a conventional system including a plurality of NV-DRAM devices is limited concerning the ease of uses thereof.